Exemplary Electronic System Level (“ESL”) Tools Improve Productivity
The complexity of integrated circuits (“ICs”) is growing exponentially. (See, e.g., Reference 1). To keep pace with this complexity, ESL computer-aided design (“CAD”) tools (e.g., also called high-level synthesis tools) are being used to design ICs. For example, 14 out of the top 20 semiconductor companies use ESL tools. (See, e.g., References 2-4). ESL tool sales were around $460 million in 2011. (See, e.g., Reference 1). The value of the ICs produced using ESL tools can be at least an order of magnitude more.
ESL design have the following advantages (see, e.g., References 4 and 5):                1) Designing at a higher level of abstraction decreases the design time. Designing an IC at ESL can be faster than designing at the register transfer level (“RTL”). (See, e.g., Reference 6-13).        2) Design specification can be simpler at higher levels of abstraction. Specifying a million-gate design in RTL requires 300K lines of code. Specifying in C/C++ reduces the complexity by up to 10 times. (See, e.g., Reference 14).        3) Design verification can be easier at higher levels of abstraction. (See, e.g., References 5 and 15).        4) Specifying the target IC and the software that will run on it in the same specification language (e.g., C/C++) facilitates exploration of hardware/software trade-offs.        
FIG. 1 shows a standard ESL design flow 100 that can begin at the designer stage 102. Specification 104 in C/C++ can be the starting point. A High-Level Description 106 can be provided to the ESL tool 108 to convert this High-Level Specification 106 into a RTL representation 110. Physical design tools can generate layout masks, which can then be sent to a foundry. The foundry can manufacture ICs which can be tested, packaged and sold.
Exemplary Globalized IC Design Introduces Security Vulnerabilities
The cost of owning a foundry in 2015 was projected to be $5 billion. (See, e.g., Reference 16). Only a small number of high-end commercial foundries remain. (See, e.g., Reference 17). Companies that do not own a foundry outsource their fabrication to these foundries. This results in security vulnerabilities. (See, e.g., References 18-23). An attacker in the foundry or a rogue user (e.g., element 110 in FIG. 1 (see, e.g., Reference 18)), can reverse engineer the functionality of an IC/IP, and then steal/claim its ownership. (See, e.g., Reference 24). An untrustworthy foundry can overbuild ICs and sell the excess illegally. (See, e.g., References 25-27). Additionally, a rogue element in a foundry can insert malicious circuits (e.g., hardware Trojans) into the design. (See, e.g., Reference 21).
To thwart attacks from rogue elements in the foundry, and from attacks from malicious users, researchers have developed procedures to harden a design. (See, e.g., References 25-27). These exemplary hardening procedures can lock the IC using a key. The IC can become functional only when the valid key can be applied, and can remain non-functional otherwise.
An exemplary Hardened Register-Transfer Level Design 114 can be generated by a designer, using various exemplary IP protection techniques 112. For example, as shown in FIG. 1, the Hardened Register-Transfer Level Design 114 can generate a Gate-Level Synthesis 115, and a Gate-Level Netlist 118. The Gate-Level Netlist 118 can be used to generate a Physical Synthesis 120 and a Layout 122. The hardened design, without the key, can then be sent to the Foundry 124 to be manufactured 126 as non-functional IC's 130. The manufactured IC's 130 can be returned to the designer 102, where they can be activated 132 as Functional IC's 134. For example, the designer can program the secret key by loading it in a tamper-evident memory. Reverse engineering 128 a hardened design can be difficult for an attacker in the foundry.
Exemplary Hardening ESL-Generated Designs
A design generated by an ESL tool can have two parts: The datapath that can consist of operators, registers, multiplexers, and the buses/wires that connect them, and the controller that can orchestrate the read and write operations between registers and operators. The controller can implement a finite state machine (“FSM”) of the design. An ESL-generated controller can have two parts: (i) the next state logic to control the state transitions, and (ii) the output logic to orchestrate the read and write operations in the current state.
An ESL-generated design can be hardened in two ways. First, the next-state logic can be hardened because without the next-state logic, the timing and source of read/write operations may not be known. In addition, controllers can be minuscule (e.g., <1% of hardware) (see, e.g., Reference 28), and hardening them can incur low power, area, and delay overhead. Alternatively, the datapath can be hardened. However, it is expensive; it can incur an approximately 25% overhead to provide reasonable security. (See, e.g., Reference 29). Thus, the state-of the-art hardening procedures can harden only the next-state logic of the controller in ESL-generated designs. (See, e.g., References 25-27).
Thus, it may be beneficial to provide an exemplary system, method and computer-accessible medium for security-centric electronic system design, which can overcome at least some of the deficiencies described herein above.